Test Planning for 3D SICs using ILP

In this paper we propose a test planning scheme for corebased 3D stacked integrated circuits where the total test cost for wafer sort of each individual chip and the test cost of the complete stack at package test is minimized. We use an Integer Linear Programming (ILP) model to find the optimal test cost, which is given as the weighted sum of the test time and the test access mechanism (TAM). As ILP is time consuming, we use a scheme to bound the test time and the TAM such that the search space is reduced. The proposed bounding scheme and the ILP model were applied on several ITC’02 benchmarks and the results show that optimal solutions were obtained at low computation time

Test Planning and Test Access Mechanism Design for 3D SICs

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips

Test Cost Reduction of 3D Stacked ICs : Test Planning and Test Flow Selection

Ever higher levels of integration within the Integrated Circuit (IC) tomeet progressively widening scope of its application in respect of functionality,size, performance and manufacturing issues inspired developmentof the three-dimensional (3D) Stacked IC as a device havingviable architecture. However, with increased complexity, manufacturingcost increased. The manufacturing cost includes the test cost component,essential to ensure fidelity to the desired design specifications.Of the several challenges faced by 3D Stacked ICs, cost efficient testingof the manufactured product is most critical. Reduction of test cost for3D Stacked ICs through test planning along with test flow selectionmethods is addressed in this thesis.Test planning for 3D Stacked ICs is performed by reducing the totalcost accounting for the test time and Design-for-Test (DfT) hardware.Three test architecture standards are used: Built-In Self-Test (BIST),IEEE 1149.1 and IEEE 1500. The test cost corresponding to each testarchitecture is detailed and test planning algorithms are proposed. Thealgorithms are implemented and experiments are performed on several3D Stacked IC designs formed with multiple 2D IC benchmarks. Forexperiment, a test flow is presented that comprises the wafer test ofeach chip followed by test of the entire packaged IC. Results indicateeffectiveness of the proposed algorithms in terms of test cost.Test flow selection, to decide stages at which tests are to be performed,for 3D Stacked ICs is addressed motivated towards the reductionof test time required to produce each single fault-free package. Amodel to calculate the total test time for any given test flow is detailed.An algorithm is proposed to find a test flow for reducing test time.The algorithm is implemented and executed on several 3D Stacked ICdesigns with up to ten chips in the stack. Results indicate considerablereductions in test time as compared to predetermined test flows

Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost

Ethical dilemmas and their solving in social work micro practice

Diplomdarba tēmas nosaukums ir „Ētiskās dilemmas un to risināšana sociālā darba mikro praksē”. Diplomdarba mērķis ir teorētiski un empīriski pētīt un analizēt ētikas dilemmas un to risināšanu sociālā darba mikro praksē. Diplomdarba ietvaros teorētiskajā daļā ir apskatīti tādi jautājumi kā sociālā darba mikro prakse, ētikas un vērtību jēdziens sociālā darba mikro praksē, ētiskās dilemmas sociālā darba mikro praksē. Darba pamatā liela uzmanība pievērsta tieši ētiskām dilemmām un to risināšanas veidiem, kā arī plašāk analizētas sociālā darba mikro prakses vērtības un ētika. Lai sasniegtu darba mērķi, autores veica empīrisko pētījumu, lai noskaidrotu, kā sociālie darbinieki risina ētiskas dilemmas un, kādas ir visbiežāk sastopamās ētiskās dilemmas sociālā darba mikro praksē. Tika noskaidrots kādas metodes sociālie darbinieki izmanto un vai ir informēti par teorētiskajām vadlīnijām ētisko dilemmu risināšanā sociālā darba mikro praksē. Pamatojoties uz iegūtajiem pētījuma rezultātiem, ir izstrādāti secinājumi un ieteikumi efektīvākas ētisko dilemmu risināšanas veicināšanai sociālā darba mikro praksē. Izstrādātie ieteikumi var palīdzēt un atvieglot sociālo darbinieku darbu ētisko dilemmu lēmumu pieņemšanā. Atslēgvārdi: ētiskās dilemmas, mikro prakse, vērtības, ētika.The subject of the Bachelor's Paper is Ethical dilemmas and their solving in social work micro practise. The aim of the Paper is to study and analyze theoretically and empirically ethic dilemmas and solving them in social work micro practice. The theoretical part of the Paper overlooks such aspects as social work micro practice, ethic dilemmas in social work, the notion of ethic and values in social work micro practice, ethic dilemmas and the ways of solving them, as well as a wide analysis of values and ethics at social work micro practice. In order to reach the aim of the Paper the authors conducted an empiric research to find out the way social workers solve ethic dilemmas and the kinds of the most frequent ethic dilemmas in social work micro practice. The authors found out the methods social workers apply and whether they are informed about the theoretical directions in solving ethic dilemmas in social work micro practice. Taking into consideration the results of the research the authors worked out conclusions and recommendations to further solving ethic dilemmas in social work micro practice. The recommendations been worked out are possible to help in solving ethic dilemmas in social work. Key words: ethic dilemmas, micro practice, values, ethics

Scheduling Tests for 3D Stacked Chips under Power Constraints

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.Funding Agencies|Swedish Research Council|

Test Flow Selection for Stacked Integrated Circuits

Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture

Test Planning for Core-based Integrated Circuits under Power Constraints

This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time